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LAN8700 Datasheet PDF : 73 Pages
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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM in a Small Footprint
Datasheet
Table 3.4 Boot Strap Configuration Inputs (Note 3.1)
SIGNAL NAME
TYPE
DESCRIPTION
RXD3/
nINTSEL
I/O nINT pin mode select: set the mode of pin 1.
Default, left floating pin 1 is nINT, active low interrupt output.
Notes:For nINT mode, tie nINT/TXD4/TXER to VDDIO with a
resistor (see Table 4.3, “Boot Strapping Configuration Resistors,”
on page 32).
Pulled to VSS by a resistor, (see Table 4.3, “Boot Strapping
Configuration Resistors,” on page 32) pin 1 is TX_ER/TXD4,
Transmit Error or Transmit data 4 (5B mode).
Notes:For TXD4/TXER mode, do not tie nINT/TXD4/TXER to
VDDIO or Ground.
Note 3.1 On nRST transition high, the PHY latches the state of the configuration pins in this table.
SIGNAL NAME
nINT/
TX_ER/
TXD4
nRST
CLKIN/
XTAL1
XTAL2
Table 3.5 General Signals
TYPE
I/O
I
I/O
O
DESCRIPTION
LAN Interrupt – Active Low output. Place an external resistor
(see Table 4.3, “Boot Strapping Configuration Resistors,” on
page 32) pull-up to VCC 3.3V.
Notes:
This signal is mux’d with TXER/TXD4
See Section 4.10, "nINT/TX_ER/TXD4 Strapping," on page 30
for additional details on Strapping options.
External Reset – input of the system reset. This signal is active
LOW.
Clock Input – 25 Mhz or 50 MHz external clock or crystal input.
In MII mode, this signal is the 25 MHz reference input clock
In RMII mode, this signal is the 50 MHz reference input clock
which is typically also driven to the RMII compliant Ethernet MAC
clock input.
Note: See Section 4.10, "nINT/TX_ER/TXD4 Strapping," on
page 30 for additional details on Strapping options.
Clock Output – 25 MHz crystal output.
Note: Float this pin if using an external clock being driven
through CLKIN/XTAL1
Revision 1.0 (02-09-07)
16
DATASHEET
SMSC LAN8700/LAN8700I
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