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LPC47M172-NW

Advanced I/O Controller with Motherboard GLUE Logic

SMSC -> Microchip 

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Chapter 3 Description of Pin Functions

PIN#

NAME

(NOTE 1)

6,31,

49,60,

123

76,93,

107,

117

See Note

71

8,29,

46,58,

78,96,

110

70

VCC

VTR

V_5P0_STBY

VSS

REF5V

72

REF5V_STBY

97

F_CAP

65

CLOCKI

91

CLOCKI32

52

nLPCPD

53

SER_IRQ

54

nLDRQ

55

PCI_CLK

56

nLFRAME

57,59, LAD[3:0]

61,62

Table 3.1 - LPC47M172 Pin Description

BUFFER

DESCRIPTION

NAME

(NOTE 2)

POWER AND GROUND PINS (20) See Note 11

+3.3 Volt Main Supply Voltage (5)

PWR

PWR

WELL

(NOTE 3)

NOTES

+3.3 Volt Standby Supply Voltage (4) See PWR

11

Note

+5 Volt Standby Supply Voltage.

Ground (7)

PWR

PWR

5V Reference Output. Requires external AO

pull-up to VCC5V.

VCC

Highest System Standby Voltage.

AO

VTR

Requires external pull-up to

V_5P0_STBY.

Internal Regulator Filter Capacitor. This

pin is a no connect. A filter capacitor can

be placed on this pin if it is required by

system board layout.

CLOCKS (2)

14.318Mhz Clock Input

IS

VCC

32.768kHz Clock Input

IS

VTR

4

PROCESSOR/HOST LPC INTERFACE (11)

Active low input Power Down signal

indicates that the LPC47M172 should

prepare for power to be shut-off on the

LPC interface.

PCI_I

VCC

5

Serial IRQ pin used with the PCI_CLK pin

to transfer LPC47M172 interrupts to the

host.

PCI_IO

VCC

Active low output used for encoded

DMA/Bus Master request for the LPC

interface.

PCI_O

VCC

33.33 MHz PCI Clock input.

PCI_ICLK VCC

Active low input indicates start of new

cycle and termination of broken cycle.

PCI_I

VCC

Active high LPC I/O used for multiplexed PCI_IO

command, address and data bus.

VCC

SMSC/Non-SMSC Register Sets (Rev. 01-11-07)

Page 14

DATASHEET

SMSC LPC47M172

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