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LPC47M192-NW

LPC Super I/O with Hardware Monitoring Block

SMSC -> Microchip 

QFP PIN#

102, 111,

121, 122

101, 112,

125, 126,

127, 128

103

104

105

106

107

108

109

110

115

116

117

118

119

120

113

114

123

124

NAME

HVCC

HVSS

SDA

SCLK

A0/

RESET#/

THERM#/

XNOR_OUT

VID0

VID1

VID2

VID3

12V_IN/

VID4

+5V_IN

+3.3V_IN

+2.5V_IN

Vccp_IN

+1.8V_IN

+1.5V_IN

D0-/

XNOR_IN

D0+

D1+

D1-

DESCRIPTION

BUFFER

NAME

HARDWARE MONITORING BLOCK (28)

+3.3V VCC pin dedicated to the Hardware

Monitoring block. Can be powered by

+3.3V Standby power if monitoring in low

power states is required.

Analog Ground. Internally connected to all

of the Hardware Monitoring Block circuitry.

PWR

WELL

NOTES

1

1

System Management Bus bi-directional

Data. Open Drain output.

System Management Bus Clock.

The lowest order programmable bit of the

SMBus Address Input.

Minimum 20msec low Reset output pulse

Interrupt output for temperature and voltage

interrupts.

XNOR-Chain test mode Output

The RESET# and THERM# are Open-Drain

Outputs

Voltage ID 0 Input

Voltage ID 1 Input

Voltage ID 2 Input

Voltage ID 3 Input

Defaults to Analog Input for +12V.

Optionally, can be configured to read the

VID4 Digital Input, a voltage supply readout

from the processor. This value is read in the

VID4 Register.

Analog input for +5V

Analog input for +3.3V

Analog input for +2.5V

Analog input for +Vccp (processor voltage:

0 to 3.0V).

Analog input for +1.8V

Analog Input for +1.5V

This is the negative Analog input (current

sink) from the remote thermal diode. This

serves as the negative input into the A/D.

Digital Input. If held high at power-up,

initiates XNOR chain test mode.

This is the positive input (current source)

from the remote thermal diode. This serves

as the positive input into the A/D.

See D0+ description.

See D0- negative analog input description.

IMOD3

IM

IMO3

IM

IM

IM

IM

IANG /IM

IANG

IANG

IANG

IANG

IANG

IANG

IANG /IM

IANG

IANG

IANG

HVCC

HVCC

HVCC

HVCC

HVCC

HVCC

HVCC

HVCC

HVCC

HVCC

HVCC

HVCC

Note:

Note 1:

Note 2:

Note 3:

The “n” as the first letter of a signal name or the “#” as the suffix of a signal name indicates an “Active Low”

signal.

VCC and VSS pins are for Super I/O Blocks. HVCC and HVSS are dedicated for the Hardware Monitoring

Block.

VTR can be connected to VCC if no wakeup functionality is required.

If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the configuration

register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is connected. This bit

determines the clock source for the fan tachometer, LED and “wake on specific key” logic. Set this bit to ‘1’

if the clock is not connected.

SMSC DS – LPC47M192

Page 19

Rev. 03/30/05

DATASHEET

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