LPC47N267(2000) Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47N267
(Rev.:2000)

100 Pin LPC Notebook I/O with X-Bus Interface

SMSC -> Microchip 

5.0 3.3 VOLT OPERATION / 5 VOLT TOLERANCE

The LPC47N267 is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that

is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.

The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are:

ƒ LAD[3:0]

ƒ LFRAME#

ƒ LDRQ#

ƒ LPCPD#

The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins:

ƒ PCI_RESET#

ƒ PCI_CLK

ƒ SER_IRQ

ƒ CLKRUN#

ƒ IO_PME#

6.0 POWER FUNCTIONALITY

The LPC47N267 has two power planes: VCC and VTR.

6.1 VCC Power

The LPC47N267 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational Description Section

and the Maximum Current Values subsection.

6.2 VTR Support

The LPC47N267 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the

PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description

Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle

Power Functionality subsection and the Maximum Current Values subsection. If the LPC47N267 is not intended to

provide wake-up capabilities on standby current, VTR can be connected to VCC. The VTR pin generates a VTR Power-

on-Reset signal to initialize these components.

Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum

potential at least 10 µs before VCC begins a power-on cycle. When VTR and VCC are fully powered, the potential

difference between the two supplies must not exceed 500mV.

6.3 Internal PWRGOOD

An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface

as VCC cycles on and off. When the internal PWRGOOD signal is “1” (active), VCC > 2.3V (nominal), and the

LPC47N267 host interface is active. When the internal PWRGOOD signal is “0” (inactive), VCC ≤ 2.3V (nominal), and

the LPC47N267 host interface is inactive; that is, LPC bus reads and writes will not be decoded.

The LPC47N267 device pins IO_PME#, nRI1, nRI2, and most GPIOs (as input) are part of the PME interface and

remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power

Functionality section.

6.4 Trickle Power Functionality

When the LPC47N267 is running under VTR only, the PME wakeup events are active and (if enabled) able to assert

the IO_PME# pin active low. The following lists the wakeup events:

ƒ UART 1 Ring Indicator

ƒ UART 2 Ring Indicator

ƒ GPIOs for wakeup. See below.

The following requirements apply to all I/O pins that are specified to be 5 volt tolerant:

ƒ I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins

may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.

SMSC DS – LPC47N267

Page 17

Rev. 10/23/2000

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