LPC47N267(2000) Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47N267
(Rev.:2000)

100 Pin LPC Notebook I/O with X-Bus Interface

SMSC -> Microchip 

7.0 FUNCTIONAL DESCRIPTION

7.1 Super I/O Registers

The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately

after power up. The base addresses of the FDC, serial and parallel ports, runtime register block and configuration

register block can be moved via the configuration registers. Some addresses are used to access more than one

register.

7.2 Host Processor Interface (LPC)

The host processor communicates with the LPC47N267 through a series of read/write registers via the LPC interface.

The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or

DMA transfers. All registers are 8 bits wide.

Table 1 - Super I/O Block Addresses

ADDRESS

Base+(0-5) and +(7)

Base+(0-7)

Base1+(0-7)

Base2+(0-7)

Base+(0-3)

Base+(0-7)

Base+(0-3), +(400-402)

Base+(0-7), +(400-402)

Base + (0-F)

Base + (0-1)

Base +(0)

Base Address = 44h

Base Address = 46h

Base Address = 48h

Base Address = 4Ah

BLOCK NAME

Floppy Disk

Serial Port Com 1

Serial Port Com 2

Parallel Port

SPP

EPP

ECP

ECP+EPP+SPP

Runtime Registers

Configuration

X-Bus

CS0

CS1

CS2

CS3

NOTES

IR Support

FIR and CIR

Note 1: Refer to the configuration register descriptions for setting the base address.

7.3 LPC Interface

The following sub-sections specify the implementation of the LPC bus.

7.3.1 LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz

electrical signal characteristics.

SIGNAL

NAME

LAD[3:0]

LFRAME#

PCI_RESET#

LDRQ#

IO_PME#

LPCPD#

SER_IRQ

PCI_CLK

CLKRUN#

TYPE

I/O

Input

Input

Output

OD

Input

I/O

Input

I/OD

DESCRIPTION

LPC address/data bus. Multiplexed command, address and data bus.

Frame signal. Indicates start of new cycle and termination of broken cycle

PCI Reset. Used as LPC Interface Reset.

Encoded DMA/Bus Master request for the LPC interface.

Power Mgt Event signal. Allows the LPC47N267 to request wakeup.

Powerdown Signal. Indicates that the LPC47N267 should prepare for power to be shut

on the LPC interface.

Serial IRQ.

PCI Clock.

Clock Run. Allows the LPC47N267 to request the stopped PCI_CLK be started.

SMSC DS – LPC47N267

Page 19

Rev. 10/23/2000

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