LPC47N267(2000) Ver la hoja de datos (PDF) - SMSC -> Microchip
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LPC47N267 Datasheet PDF : 180 Pages
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GENERAL DESCRIPTION
The SMSC LPC47N267 is a 3.3V PC 99 and ACPI 1.0 compliant Super I/O Controller. The LPC47N267 implements
an LPC interface, a pin reduced ISA interface, for supported I/O and DMA cycles. In addition, this part includes an X-
Bus interface that may be accessed through the LPC interface for supported I/O cycles (memory cycles are not
supported by this device). The X-Bus interface supports as many as four external components and it offers three
different modes of operation for interfacing with these components. The X-Bus interface has an added “Write
Protect” feature that ensures that the Base Address and disable bit for each component can only be set by the BIOS
to prevent corruption by any virus software. This part also includes 29 GPIO pins.
The LPC47N267 incorporates SMSC’s true CMOS 765B floppy disk controller, advanced digital data separator, 16-
byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port with ChiProtect circuitry plus EPP and
ECP support and one floppy direct drive support. The LPC47N267 does not require any external filter components, is
easy to use and offers lower system cost and reduced board area. The LPC47N267 is software and register
compatible with SMSC’s proprietary 82077AA core.
The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and provides data
overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC’s patented data
separator technology allowing for ease of testing and use. The LPC47N267 supports both 1Mbps and 2Mbps data
rates and vertical recording operation at 1Mbps Data Rate.
The LPC47N267 also features a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI nCLKRUN
support, relocatable configuration ports and three DMA channel options.
Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial Infrared
Interface that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats (used by Sharp and other PDAs), as well
as Consumer IR.
The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The parallel port
ChiProtect circuitry prevents damage caused by an attached powered printer when the LPC47N267 is not powered.
The LPC47N267 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power
down modes. The LPC47N267 also features Software Configurable Logic (SCL) for ease of use. SCL allows
programmable system configuration of key functions such as the FDC, parallel port, and UARTs.
The LPC47N267 supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended
functionaity to support Windows ‘95/’98 and PC99. The I/O Address, DMA Channel and Hardware IRQ of each
device in the LPC47N267 may be reprogrammed through the internal configuration registers. There are 192 I/O
address location options, a Serialized IRQ interface, and three DMA channels.
ORDERING INFORMATION
Order Number: LPC47N267-MN
for 100 pin STQFP Package
SMSC DS – LPC47N267
Page 3
Rev. 10/23/2000
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