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LPC47N237

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC -> Microchip 

General Description

The LPC47N237 is a 3.3V (5V Tolerant) PC99a/PC2001 compliant Docking I/O controller. The device,

which implements the LPC interface, includes I/O functionality. LPC47N237’s LPC interface supports LPC

I/O and DMA cycles. There is also a SMBus hosted GPIO Block.

The LPC47N237 provides 4 LPC general purpose pins which offer flexibility to the system designer. The

legacy I/O included in the LPC47N237 are: a 16C550A compatible UART; one Multi-Mode parallel port

including ChiProtect circuitry plus EPP and ECP. The parallel port is compatible with IBM PC/AT

architecture, as well as IEEE 1284 EPP and ECP. The LPC47N237 incorporates sophisticated power

control circuitry (PCC) which includes support for PME. The PCC supports multiple low power-down

modes. The LPC47N237 is ACPI 1.0b/2.0 compatible.

The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47N237 may be

reprogrammed through the internal configuration registers. There are up to 480 (960 for Parallel Port) I/O

address location options, a Serialized IRQ interface, and three DMA channels.

The SMBus hosted GPIO Block includes 32 GPIOs that are powered by standby supply. The GPIOs can

be used to assert an interrupt on a change in state of a GPIO. These events are indicated on the

nSMBINT pin.

IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business

Machines Corporation.

SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard

Microsystems Corporation.

SMSC DB – LPC47N237

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PRODUCT PREVIEW

Revision 0.3 (03-30-07)

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