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LT1964 Datasheet PDF : 12 Pages
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LT1964
PI FU CTIO S
collector logic with a pull-up resistor. The pull-up resistor
is required to supply the pull-up current of the open
collector gate, normally several microamperes, and the
SHDN pin current, typically 3µA out of the pin (for negative
logic) or 6µA into the pin (for positive logic). If unused,
the SHDN pin must be connected to VIN. The device will
be shut down if the SHDN pin is open circuit. For the
LT1964-BYP, the SHDN pin is internally connected to VIN.
A parasitic diode exists between the SHDN pin and the
input of the LT1964. The SHDN pin cannot be pulled more
negative than the input during normal operation, or more
than 0.5V below the input during a fault condition.
ADJ (Pin 4, Adjustable Devices only): For the Adjustable
LT1964, this is the Input to the Error Amplifier. The ADJ pin
has a bias current of 30nA that flows out of the pin. The
ADJ pin voltage is –1.22V referenced to ground, and the
output voltage range is –1.22V to –20V. A parasitic diode
exists between the ADJ pin and the input of the LT1964.
The ADJ pin cannot be pulled more negative than the input
during normal operation, or more than 0.5V more negative
than the input during a fault condition.
OUT (Pin 5): The Output Supplies Power to the Load. A
minimum output capacitor of 1µF is required to prevent
oscillations. Larger output capacitors will be required for
applications with large transient loads to limit peak voltage
transients. A parasitic diode exists between the output and
the input. The output cannot be pulled more negative than
the input during normal operation, or more than 0.5V
below the input during a fault condition. See the Applica-
tions Information section for more information on output
capacitance and reverse output characteristics.
APPLICATIO S I FOR ATIO
The LT1964 is a 200mA negative low dropout regulator
with micropower quiescent current and shutdown. The
device is capable of supplying 200mA at a dropout voltage
of 340mV. Output voltage noise can be lowered to 30µVRMS
over a 10Hz to 100kHz bandwidth with the addition of a
0.01µF reference bypass capacitor. Additionally, the refer-
ence bypass capacitor will improve transient response of
the regulator, lowering the settling time for transient load
conditions. The low operating quiescent current (30µA)
drops to 3µA in shutdown. In addition to the low quiescent
current, the LT1964 incorporates several protection
features which make it ideal for use in battery-powered
systems. In dual supply applications where the regulator
load is returned to a positive supply, the output can be
pulled above ground by as much as 20V and still allow the
device to start and operate.
Adjustable Operation
The adjustable version of the LT1964 has an output voltage
range of –1.22V to –20V. The output voltage is set by the
ratio of two external resistors as shown in Figure 1. The
device servos the output to maintain the voltage at the ADJ
pin at –1.22V referenced to ground. The current in R1 is
then equal to –1.22V/R1 and the current in R2 is the
current in R1 plus the ADJ pin bias current. The ADJ pin
bias current, 30nA at 25°C, flows through R2 out of the
ADJ pin. The output voltage can be calculated using the
formula in Figure 1. The value of R1 should be less than
250kto minimize errors in the output voltage caused by
the ADJ pin bias current. Note that in shutdown the output
is turned off and the divider current will be zero. Curves of
ADJ Pin Voltage vs Temperature and ADJ Pin Bias Current
vs Temperature appear in the Typical Performance Char-
acteristics section.
The adjustable device is tested and specified with the ADJ
pin tied to the OUT pin and a 5µA DC load (unless otherwise
specified) for an output voltage of –1.22V. Specifications
for output voltages greater than –1.22V will be propor-
tional to the ratio of the desired output voltage to –1.22V;
(VOUT/– 1.22V). For example, load regulation for an output
current change of 1mA to 200mA is 2mV typical at VOUT =
–1.22V. At VOUT = –12V, load regulation is:
(–12V/–1.22V) • (2mV) = 19.6mV
1964f
8

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