LTC2202I(RevB) Ver la hoja de datos (PDF) - Linear Technology
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LTC2202I Datasheet PDF : 32 Pages
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LTC2203/LTC2202
APPLICATIO S I FOR ATIO
the new sample is small, the charging glitch seen at the
input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specified performance. Each input may
swing ±0.625V for the 2.5V range (PGA = 0) or ±0.417V
for the 1.667V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 3) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2µF or greater.
Input Drive Impedence
As with all high performance, high speed ADCs the
dynamic performance of the LTC2203/LTC2202 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and
input reactance can influence SFDR. At the rising edge of
CLK the sample and hold circuit will connect the 9.1pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when CLK falls, hold-
ing the sampled input on the sampling capacitor. Ideally,
the input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FCLK); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recomended to have a source
impedence of 100Ω or less for each input. The source
impedence should be matched for the differential inputs.
Poor matching will result in higher even order harmonics,
especially the second.
INPUT DRIVE CIRCUITS
Figure 3 shows the LTC2203/LTC2202 being driven by
an RF transformer with a center-tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Figure 3 shows
20
a 1:1 turns ratio transformer. Other turns ratios can be
used; however, as the turns ratio increases so does the
impedance seen by the ADC. Source impedance greater
than 50Ω can reduce the input bandwidth and increase
high frequency distortion. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
VCM
T1
ANALOG
1:1
INPUT
12pF
AIN+
12pF
LTC2203/02
AIN–
T1 = COILCRAFT WBCI-IT OR
MA/COM ETC1-1T.
RESISTORS, CAPACITORS ARE
0402 PACKAGE SIZE, EXCEPT 2.2μF.
12pF
22032 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 1MHz to 100MHz
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
Figure 4 shows transformer coupling using a transmis-
sion line balun transformer. This type of transformer has
much better high frequency response and balance than flux
coupled center tap transformers. Coupling capacitors are
added at the ground and input primary terminals to allow
the secondary terminals to be biased at 1.25V.
VCM
0.1μF
ANALOG
INPUT
T1
1:1
0.1μF
0.1μF
2.2μF
AIN+
LTC2203/02
4.7pF
4.7pF
AIN–
T1 = MA/COM ETC1-1-13.
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE,
EXCEPT 2.2F.
4.7pF
22032 F04
Figure 4. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 50MHz to 250MHz
22032fb
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