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SM5838AS

5120 × 8-bit Synchronous FIFO

Nippon Precision Circuits  

SM5838AS

Write Cycle

The input data address is determined by the write

address pointer position. The write address pointer is

reset by RW (write reset cycle), and is incremented

on the rising edge of CLK whenever WE is LOW.

Data input occurs on the rising edge of CLK at the

end of the write cycle.

When WE goes HIGH, write operation is disabled

and the write address pointer stops.

n cycle

t CKW

n+1 cycle

disable cycle

n+2 cycle

CLK

t CKW

t WEH

t WES

t WEH

t WES

WE

t DS

t DS

DIN (n-1) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

(n) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (n+1) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

(n+2)

t DH

t DH

RW="H"

Read Cycle

The output data address is determined by the read

address pointer position. The read address pointer is

reset by RR (read reset cycle), and is incremented on

the rising edge of CLK whenever RE is LOW. Data

output starts tA (max) after the rising edge of CLK at

the start of the read cycle and continues until tOH

(min) after the next rising edge of CLK.

When RE goes HIGH, read operation is disabled and

the read address pointer stops.

Note that data being read was written at least 20

write cycles previously (FIFO minimum delay).

Therefore, if (write address pointer) − (read address

pointer) = 1 to 19, then a possibility exists that data

from the preceding line is output instead.

CLK

n cycle

t CKW

t CKW

RE

tA

DOUT (n-1) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

(n)

n+1 cycle

t REH

t RES

tA

,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

(n+1)

t OH

disable cycle

n+2 cycle

t REH

t RES

tA

,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

(n+2)

t OH

RR="H" , OE="L"

NIPPON PRECISION CIRCUITS—7

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