M2V64S20BTP Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
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M2V64S20BTP Datasheet PDF : 52 Pages
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SDRAM (Rev.1.2)
Apr. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same
cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start
address is specified by A9-0 (x 4), A8-0 (x 8) and A7-0 (x 16), and the address sequence of burst data is
defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge
time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last
input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE
command, the auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhib-ited till the internal precharge is complete. The internal precharge begins at tWR after the
last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing.
The Mode Register can be programmed for burst read and single write. In this mode the write data is only
clocked in when the WRITE command is issued and the remaining burst length is ignored. The read data
burst length os unaffected while in this mode
Multi Bank Interleaving WRITE (BL=4)
CLK
Command
A0-9
A10
A11
BA0,1
DQ
CLK
ACT
Xa
tRCD
Write ACT
Y Xb
tRCD
Write PRE
Y
PRE
Xa
0 Xb
0
0
0
Xa
Xb
0
0
00
00 10
10 00
10
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
WRITE with Auto-Precharge (BL=4)
Command
A0-9
A10
A11
BA0,1
DQ
ACT
Xa
tRCD
Write
Y
tWR
ACT
tRP
Xa
Xa
1
Xa
Xa
Xa
00
00
00
Da0 Da1 Da2 Da3
Internal precharge starts
MITSUBISHI ELECTRIC
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