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M2V28S20ATP-6

128M Synchronous DRAM

Mitsumi 

SDRAM (Rev. 1.0E)

Nov. '99

MITSUBISHI LSIs

128M Synchronous DRAM

M2V28S20ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 8,388,608-WORD x 4-BIT)

M2V28S30ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 8-BIT)

M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT)

SIMPLIFIED STATE DIAGRAM

SELF

REFRESH

MODE

REGISTER

SET

MRS

REFS

REFSX

IDLE

REFA

AUTO

REFRESH

CKEL

CLK

SUSPEND

CKEH

ACT

CKEL

POWER

DOWN

CKEH

WRITE

ROW

ACTIVE

READ

WRITE CKEL

SUSPEND

WRITE

CKEH

WRITEA READA

READ

WRITE

READ

CKEL READ

SUSPEND

CKEH

WRITEA

WRITEA READA

CKEL

WRITEA

WRITEA

SUSPEND

CKEH

PRE

PRE

PRE

READA

CKEL

READA

READA

SUSPEND

CKEH

POWER

APPLIED

POWER PRE

ON

PRE

CHARGE

Automatic Sequence

Command Sequence

MITSUBISHI ELECTRIC

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