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M2V28S20ATP-6

128M Synchronous DRAM

Mitsumi 

SDRAM (Rev. 1.0E)

Nov. '99

MITSUBISHI LSIs

128M Synchronous DRAM

M2V28S20ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 8,388,608-WORD x 4-BIT)

M2V28S30ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 8-BIT)

M2V28S40ATP -6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 16-BIT)

CLK

Command

Address

DQ

Read

Y

Q0 Q1 Q2 Q3

Write

Y

D0 D1 D2 D3

CL= 3

BL= 4

/CAS Latency

Burst Length

Burst Type

Burst Length

Initial Address BL

Column Addressing

A2 A1 A0

Sequential

Interleaved

00 0

0 1 23 4 56 7 01 2 34 5 6 7

00 1

1 2 34 5 67 0 10 3 25 4 7 6

01 0

2 3 45 6 70 1 23 0 16 7 4 5

01 1

3 4 56 7 01 2 32 1 07 6 5 4

8

10 0

4 5 67 0 12 3 45 6 70 1 2 3

10 1

5 6 70 1 23 4 54 7 61 0 3 2

11 0

6 7 01 2 34 5 67 4 52 3 0 1

11 1

7 0 12 3 45 6 76 5 43 2 1 0

- 00

0 1 23

01 2 3

- 01

1 2 30

4

- 10

2 3 01

10 3 2

23 0 1

- 11

3 0 12

32 1 0

-- 0

01

2

-- 1

10

01

10

MITSUBISHI ELECTRIC

16

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