Software Wait
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software wait
The wait bit (bit 7) of the processor mode register 1 (address 000516)(note) allows you to insert software
wait states for the internal ROM/RAM areas. If this bit is 0, the bus cycle is executed in one BCLK (internal
clock) period; if the bit is 1, the bus cycle is executed in two BCLK periods. This bit is cleared to 0 after a
reset.
The SFR area is unaffected by this control bit; it is always accessed in two BCLK periods.
Table 1.2 shows the relationship between software wait states and bus cycles.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 1.2. Software waits and bus cycles
Area
Wait bit
Bus cycle
SFR
Invalid
Internal
0
ROM/RAM
1
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
17