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IRU1050CP

5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR

International Rectifier 

IRU1050

Assuming the following specifications:

VIN = 5V

VOUT = 3.5V

IOUT(MAX) = 4.6A

TA = 358C

The steps for selecting a proper heat sink to keep the

junction temperature below 1358C is given as:

1) Calculate the maximum power dissipation using:

PD = IOUT3(VIN - VOUT)

PD = 4.63(5 - 3.5) = 6.9W

2) Select a package from the regulator data sheet and

record its junction to case (or tab) thermal resistance.

Selecting TO-220 package gives us:

uJC = 2.78C/W

3) Assuming that the heat sink is black anodized, cal-

culate the maximum heat sink temperature allowed:

Assume, ucs=0.05°C/W (heat-sink-to-case thermal

resistance for black anodized)

TS = TJ - PD3(uJC + uCS)

TS = 135 - 6.93(27 + 0.05) = 1168C

4) With the maximum heat sink temperature calculated

in the previous step, the heat-sink-to-air thermal re-

sistance (uSA) is calculated by first calculating the

temperature rise above the ambient as follows:

DT = TS - TA = 116 - 35 = 818C

∆T = Temperature Rise Above Ambient

uSA

=

DT

PD

=

81

6.9

=

11.78C/W

5) Next, a heat sink with lower uSA than the one calcu-

lated in Step 4 must be selected. One way to do this

is to simply look at the graphs of the “Heat Sink Temp

Rise Above the Ambient” vs. the “Power Dissipation”

and select a heat sink that results in lower tempera-

ture rise than the one calculated in previous step.

The following heat sinks from AAVID and Thermalloy

meet this criteria.

Thermalloy

AAVID

Air Flow (LFM)

0

100 200 300 400

6021PB 6021PB 6073PB 6109PB 7141D

534202B 534202B 507302 575002 576802B

Note: For further information regarding the above com-

panies and their latest product offerings and application

support contact your local representative or the num-

bers listed below:

AAVID.................PH# (603) 528 3400

Thermalloy...........PH# (214) 243-4321

Designing for Microprocessor Applications

As it was mentioned before, the IRU1050 is designed

specifically to provide power for the new generation of

the low voltage processors requiring voltages in the range

of 2.5V to 3.6V generated by stepping down the 5V sup-

ply. These processors demand a fast regulator that sup-

ports their large load current changes. The worst case

current step seen by the regulator is anywhere in the

range of 1 to 7A with the slew rate of 300 to 500ns which

could happen when the processor transitions from “Stop

Clock” mode to the “Full Active” mode. The load current

step at the processor is actually much faster, in the or-

der of 15 to 20ns, however, the decoupling capacitors

placed in the cavity of the processor socket handle this

transition until the regulator responds to the load current

levels. Because of this requirement the selection of high

frequency low ESR and low ESL output capacitor is

imperative in the design of these regulator circuits.

Figure 5 shows the effects of a fast transient on the

output voltage of the regulator. As shown in this figure,

the ESR of the output capacitor produces an instanta-

neous drop equal to the (DVESR=ESR3DI) and the ESL

effect will be equal to the rate of change of the output

current times the inductance of the capacitor. (DVESL

=L3DI/Dt). The output capacitance effect is a droop in

the output voltage proportional to the time it takes for

the regulator to respond to the change in the current,

(DVc=Dt3DI/C) where Dt is the response time of the

regulator.

Rev. 1.8

08/20/02

www.irf.com

5

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