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IRU1050CP

5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR

International Rectifier 

IRU1050

V ESR

V ESL

T

LOAD

CURRENT

VC

1050plt1-1.0

LOAD CURRENT RISE TIME

Figure 5 - Typical regulator response

to the fast load current step.

An example of a regulator design to meet the Intel P54C™

VRE specification is given below.

2) The output capacitance is 531500mF = 7500mF

DVc = Dt 3 DI = 2 3 4.6 = 1.2mV

C

7500

Where:

Dt = 2ms is the regulator response time

To set the output DC voltage, we need to select R1 and

R2:

3) Assuming R1=121V, 0.1%:

( ) ( ) R2 =

VOUT

VREF

-1

3R1 =

3.5 -1

1.25

3121 = 217.8V

Select R2=218V, 0.1%

Assume the specification for the processor as shown in

Table 1:

Type of

Processor

Intel-P54C VRE

V OUT

Nominal

3.50 V

IMAX

Max Allowed

Output Tolerance

4.6 A

±100 mV

Selecting both R1 and R2 resistors to be 0.1% toler-

ance, results in the least amount of error introduced

by the resistor dividers leaving ≈ ±1.3% error budget

for the IRU1050 reference which is within the initial

accuracy of the device.

Table 1 - Processor Specification

Finally, the input capacitor is selected as follows:

The first step is to select the voltage step allowed in the

output due to the output capacitor’s ESR:

1) Assuming the regulator’s initial accuracy plus the re-

sistor divider tolerance is ≈ ±53mV (±1.5% of 3.5V

nominal), then the total step allowed for the ESR and

the ESL is −47mV.

Assuming that the ESL drop is −10mV, the remain-

ing ESR step will be −37mV. Therefore the output

capacitor ESR must be:

ESR

[

37

4.6

=

8mV

The Sanyo MVGX series is a good choice to achieve

both price and performance goals. The 6MV1500GX,

1500mF, 6.3V has an ESR of less than 36mV typi-

cal. Selecting 5 of these capacitors in parallel has an

ESR of ≈ 7.2mV which achieves our design goal.

4) Assuming that the input voltage can drop 150mV be-

fore the main power supply responds, and that the

main power supply response time is ≈ 50ms, then

the minimum input capacitance for a 4.6A load step

is given by:

CIN

=

4.6 3 50

0.15

= 1530mF

The ESR should be less than:

ESR = (VIN - VOUT - DV - VDROP)

DI

Where:

VDROP L Input voltage drop allowed in step 4

DV L Maximum regulator dropout voltage

DI L Load current step

(5 - 3.5 - 1.2 - 0.15)

ESR =

= 0.032V

4.6

The next step is to calculate the drop due to the ca-

pacitance discharge and make sure that this drop in

voltage is less than the selected ESL drop in the

previous step.

Selecting two Sanyo 1500mF, the same type as the

output capacitors, meets our requirements.

6

www.irf.com

Rev. 1.8

08/20/02

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