M68AW512 Ver la hoja de datos (PDF) - STMicroelectronics
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M68AW512 Datasheet PDF : 22 Pages
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M68AW512D
SUMMARY DESCRIPTION
The M68AW512D is an 8 Mbit (8,388,608 bit)
CMOS SRAM, organized as 524,288 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has a Chip
Select pin (E2) for easy memory expansion; when
it is active (E2 high) the device has an automatic
power-down feature, reducing the power con-
sumption by over 99%.
The M68AW512D is available in TFBGA48 (0.75
mm ball pitch) package.
Figure 2. Logic Diagram
VCC
19
A0-A18
W
E1
E2
G
UB
LB
16
DQ0-DQ15
M68AW512D
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ15 Data Input/Output
E1
Chip Enable
E2
Chip Select
G
Output Enable
W
Write Enable
UB
Upper Byte Enable Input
LB
Lower Byte Enable Input
VCC
Supply Voltage
VSS
Ground
NC
Not Connected
DU
Don’t Use as Internally Connected
VSS
AI04800b
4/22
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