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M68AW512

8 Mbit (512K x16) 3.0V Asynchronous SRAM

STMicroelectronics 

M68AW512D

OPERATION

The device has four standard operating modes:

Output Disabled, Read, Write and Standby/Pow-

er-Down. These modes are determined by the

control inputs E1, E1, W, G, LB and UB as sum-

marized in Table 2.Operating Modes.

Output Disabled

The Output Enable signal, G, provides high-speed

tri-state control of DQ0-DQ15, allowing fast read/

write cycles on the I/O data bus. The device is in

Output Disabled mode when Output Enable, G, is

High. In this mode, LB and UB are Don’t care and

DQ0-DQ15 are high impedance.

Read Mode

When Chip Select (E2) is High, the Mvvvvv is in

the Read mode whenever Write Enable (W) is

High with Output Enable (G) Low, and Chip En-

able (E1) is asserted.

This provides access to data from eight or sixteen,

depending on the status of the signal UB and LB,

of the 8,388,608 locations in the static memory ar-

ray, specified by the 19 address inputs. If only one

of the Byte Enable inputs is at VIL, the Mvvvvv is in

Byte Read mode. If the two Byte Enable inputs are

at VIL, the Mvvvvv is in Word Read mode. So de-

pending on the status of the UB and LB signals,

valid data will be available on the lower eight, the

upper eight or all sixteen output pins, tAVQV after

the last stable address, providing G is Low, E1 is

Low and E2 is High.

If either of E1 or G is asserted after tAVQV has

elapsed, data access will be measured from the

limiting parameter (tELQV, tGLQV or tBLQV) rather

than the address. Data out may be indeterminate

at tELQX, tGLQX and tBLQX, but data lines will al-

ways be valid at tAVQV.

Write Mode

The M68AW512D, when Chip Select (E2) is High,

is in the Write Mode whenever the W and E1 are

Low. Either the Chip Enable Input (E1) or the Write

Enable input (W) must be de-asserted during Ad-

dress transitions for subsequent write cycles.

When E1 or W is Low, and UB or LB is Low, write

cycle begins on the W or E1 falling edge. When E1

and W are Low, and UB = LB = High, write cycle

begins on the first falling edge of UB or LB. There-

fore, address setup time is referenced to Write En-

able, Chip Enables and UB/LB as tAVWL, tAVEL and

tAVBL respectively, and is determined by the latter

occurring falling edge.

The Write cycle can be terminated by the earlier

rising edge of E1, W, UB and LB.

If the Output is enabled (E1 = Low, E2 = High, G =

Low, LB or UB = Low), then W will return the out-

puts to high impedance within tWLQZ of its falling

edge. Care must be taken to avoid bus contention

in this type of operation. Data input must be valid

for tDVWH before the rising edge of Write Enable,

or for tDVEH before the rising edge of E1 or for tD-

VBH before the rising edge of UB/LB, whichever

occurs first, and remain valid for tWHDX, tEHDX and

tBHDX respectively.

Standby/Power-Down

The M68AW512D has a Chip Enable power down

feature which invokes an automatic standby mode

whenever Chip Enable is de-asserted (E1 = High)

or Chip Select is asserted (E2 = Low), or UB/LB

are de-asserted (UB/LB = High). An Output En-

able (G) signal provides a high speed tri-state con-

trol, allowing fast read/write cycles to be achieved

with the common I/O data bus. Operational modes

are determined by device control inputs W, E1, LB

and UB as summarized in the Operating Modes ta-

ble (see Table 2).

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