T15V2M16B-55S Ver la hoja de datos (PDF) - Taiwan Memory Technology

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T15V2M16B-55S

128K X 16 LOW POWER CMOS STATIC RAM

Taiwan Memory Technology 

tm TE

CH

WRITE CYCLE 3 ( UB , LB Controlled)

Ad d res s

UB / LB

CE

WE

tWC

tAW

tCW

tAS

tWP

tWR

DOUT

DIN

High-Z

High-Z

tDW

tDH

T15V2M16B

High-Z

DON'T CARE

UNDEFINED

NOTES ( WRITE CYCLE ) :

1. A write occurs during the overlap of a low CE , a low WE . A write begins at the lateat

transition among CE goes low, WE going low. A write end at the earliest transition among

CE going high, WE going high. tWP is measured from the beginning of write to the end of

write.

2. tCW is measured from the later of CE going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change.

TM Technology Inc. reserves the right

P. 9

to change products or specifications without notice.

Publication Date: NOV. 2002

Revision:A

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