M95040-SBN3T Ver la hoja de datos (PDF) - STMicroelectronics

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M95040-SBN3T

4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95040, M95020, M95010

INSTRUCTIONS

Each instruction starts with a single-byte code, as

summarized in Table 4.

If an invalid instruction is sent (one not contained

in Table 4), the device automatically deselects it-

self.

Figure 8. Write Enable (WREN) Sequence

Table 4. Instruction Set

Instruc

tion

Description

Instruction

Format

WREN Write Enable

0000 X110

WRDI Write Disable

0000 X100

RDSR Read Status Register

0000 X101

WRSR Write Status Register

0000 X001

READ Read from Memory Array

0000 A8011

WRITE Write to Memory Array

0000 A8010

Note: 1. A8 = 1 for the upper half of the memory array of the

M95040, and 0 for the lower half, and is Don’t Care for

other devices.

2. X = Don’t Care.

S

01234567

C

Instruction

D

High Impedance

Q

AI01441D

Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set pri-

or to each WRITE and WRSR instruction. The only

way to do this is to send a Write Enable instruction

to the device.

As shown in Figure 8, to send this instruction to the

device, Chip Select (S) is driven Low, and the bits

of the instruction byte are shifted in, on Serial Data

Input (D). The device then enters a wait state. It

waits for a the device to be deselected, by Chip

Select (S) being driven High.

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