M95040-SBN3T Ver la hoja de datos (PDF) - STMicroelectronics
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M95040-SBN3T Datasheet PDF : 33 Pages
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M95040, M95020, M95010
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 4 shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
Figure 4. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SDO
SDI
SCK
CS3 CS2 CS1
CQD
CQD
CQD
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
S
W HOLD
S
W HOLD
S
W HOLD
AI03746D
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
For these two modes, input data is latched in on
SPI Modes
the rising edge of Serial Clock (C), and output data
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
is available from the falling edge of Serial Clock
(C).
following modes:
The difference between the two modes, as shown
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
in Figure 5, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
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