MB86613S Ver la hoja de datos (PDF) - Fujitsu
Número de pieza
componentes Descripción
Lista de partido
MB86613S Datasheet PDF : 134 Pages
| |||
Preliminary
31
24 23
16 15
87
0
offsetLo
Bit
----
31:0
Field Name
rwu
-------------- ----
offsetLo
ru
reset
--------
undefined
description
------------------------------------------
Stores the lower 32- bit of offset_address written in the
packet that caused an error during the packet receive.
3.2.11. Vendor ID
This register indicates the vender ID of the 1394 Open HCI acquired from the Registration Authority Commit-
tee (RAC). This bits indicate “000000”h because this MB86613S is complied with the OHCI.
31
24 23
vendorUnique
16 15
87
0
vendorCompanyID
Bit
Field Name
rwu
---- -------------- ----
31:24 vendorUnique
r
23:0 vendorCompanyID r
reset
description
-------- ------------------------------------------
00h
These bits indicate ”00h”.
000000h These bits indicate “000000h”.
3.2.12. HCControl
This register controls the host operation conditions such as byte- swap and link enable.
noByteSwapData and PostedWriteEnable bits must be set when the linkEnable is not set.
MB86613S contains PHY and LINK connected together inside of the chip. So, software can not control the
performance between PHY and LINK. Therefore, programPhyEnable bit indicates ”0” and aPhyEnhanceEn-
able bit indicates ”1”. When a ”disconnect” is found in the 1394 network, the device automatically clears the
linkEnable bit. Do not set linkEnable bit before Configuration ROM mapping register is set.
As D1 state of PCI power management doesn’t supported, ackTaedyEnable bit is reserved.
31
24 23
16 15
87
0
ackTardyEnable
noByteSwapData
softReset
linkEnable
postedWriteEnable
LPS
BIBimageValid
aPhyEnhanceEnable
programPhyEnable
33
Share Link: 