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MB86613S

IEEE1394 Open HCI Controller

Fujitsu 

Preliminary

3.2.19. IsoRecvIntEvent/Mask

This register indicates the result of each context program operation for IR- CPC. When the context program

process completed and ” i ” field at context program is set to ”11b”, the applied channel indicates ”1”.

IntEvent.isochRx bit indicates the OR operation output with each bit in this register.

Also, the register read value from the IsoRecvIntEventClear indicates AND operation output between the

IsoRecvIntEvent register and IsoRecvIntMask register.

31

24 23

16 15

87

0

isoRecv30

isoRecv31

........................................................................................

isoRecv0

isoRecv1

Bit

----

31:4

3:0

Field Name

rscu

-------------- ----

isoRecv31:4

r

isoRecv3:0

rscu

reset

description

-------- ------------------------------------------

000_0000h Since the device contains only 4channels of context

program controller, these bits are fixed with ”0”.

undefined Each controller processes the context program and ”1” is

indicated in the corresponding bit when the isochronous

packet is completely received.

3.2.20. FairnessControl

This register contains and indicates the maximum execution count of priority request to transmit an asynchro-

nous request packet. Software needs to support and implement the priority budget register defined in P1394a

standard. The on- chip LINK layer loads the value specified in pri_req field in this register before activating the

fairness interval and decrements the value every execution of priority request.

This register keeps the previous value with the software reset (HCControl.softReset).

31

24 23

16 15

87

0

pri_req

Bit

----

7:0

Field Name rwu reset

--------------

----

pri_req rw

undefined

description

--------

--------------------------------------

These bits specify the maximum number of priority request

39

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