MC100EP105(2002) Ver la hoja de datos (PDF) - ON Semiconductor

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MC100EP105
(Rev.:2002)

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

ON Semiconductor 

MC10EP105, MC100EP105

Driver

Device

Q

Q

50 Ω

D

Receiver

Device

D

50 Ω

VTT

VTT = VCC – 2.0 V

Figure 4. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 – Termination of ECL Logic Devices.)

Resource Reference of Application Notes

AN1404

AN1405

AN1406

AN1504

AN1568

AN1650

AN1672

AND8001

AND8002

AND8009

AND8020

– ECLinPS Circuit Performance at Non–Standard VIH Levels

– ECL Clock Distribution Techniques

– Designing with PECL (ECL at +5.0 V)

– Metastability and the ECLinPS Family

– Interfacing Between LVDS and ECL

– Using Wire–OR Ties in ECLinPS Designs

– The ECL Translator Guide

– Odd Number Counters Design

– Marking and Date Codes

– ECLinPS Plus Spice I/O Model Kit

– Termination of ECL Logic Devices

For an updated list of Application Notes, please see our website at http://onsemi.com.

http://onsemi.com

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