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MC145532

ADPCM Transcoder

Motorola => Freescale 

APD

Absolute Power Down (Pin 9)

A logic 1 applied to this input forces the transcoder into a

power saving mode. This pin has a CMOS compatible input.

POWER SUPPLY

VDD

Positive Power Supply (Pin 16)

The most positive power supply pin, normally 5 V.

VSS

Negative Power Supply (Pin 8)

The most negative power supply pin, normally 0 V.

FUNCTIONAL DESCRIPTION

ENCODING/DECODING RATES

The MC145532 allows for the encoding and decoding of

data at one of four rates on a sample–by–sample basis.

Each data sample that is provided to the part is accompanied

by an indication of the rate at which it is to be encoded or

decoded. The width of the enable pulse determines the

encoding/decoding rate chosen for each sample.

The 64 kbps rate allows for PCM data to be passed directly

through the part. The 32 kbps rate is either the G.721–1988

or the T1.301–1987 standard, depending on the state of the

mode pin. The 24 kbps encoding rate is compliant with

CCITT G.723–1988 and G.726. The 16 kbps rate is a modi-

fied quantizer from the 32 kbps technique and is not a stan-

dard.

TIMING

Figures 1 through 8 show the timing of the input and output

pins. The MC145532 determines the mode of the timing sig-

nals, either short or long frame, for each enable, independent

of the mode of any previous enables. A transition from short

frame to long frame mode or vice versa will cause at least

one frame of data to be destroyed. Each of the four sets of

I/O pins determines its mode independent of the other sets.

Thus the encoder input could be operating with long frame

timing and the output could be operating with short frame tim-

ing. Note that the short frame timing on the input enables can

only be used with the 32 kbps transcoding rate. The number

of data clock falling edges enclosed by the input enable line

(EIE or DIE) determines both the short frame or long frame

mode and the transcoding rate. The mode of the input or out-

put is determined each frame. In all modes, the data is cap-

tured by the MC145532 on the falling edge of either EDC or

DDC.

ENCODER INPUT — SHORT FRAME

Figure 1 shows the timing of the encoder data clock

(EDC), the encoder input enable (EIE), and the encoder data

input (EDI) pins in short frame operation.

The determination of short frame mode is made by the

MC145532 based on one falling EDC edge while EIE is high.

Note that only a 32 kbps encoding rate can be specified

when using short frame mode on the encoder input.

ENCODER INPUT — LONG FRAME

Figure 2 shows the clock, enable, and data signals for the

encoder input in long frame mode. In this mode, the data is

captured by the MC145532 on the falling edge of EDC.

The determination of the encoding rate is made based on

the number of falling EDC edges seen by the MC145532

while EIE is high. Four edges implies a 32 kbps encoding

rate, three edges implies a 24 kbps encoding rate, two edges

implies a 16 kbps rate, and from five to eight inclusive imply

a 64 kbps rate. The encoding rate may be changed on a

frame–by–frame basis. The encoded word is available at

EDO (via EOE and EDC) from 250 µs to 375 µs after it is re-

quested.

ENCODER OUTPUT — SHORT FRAME

Figure 3 shows the timing of the encoder output in short

frame mode. The length of the LSB is always one half of an

EDC cycle.

The EDO will provide the correct number of bits for the en-

coding rate that was selected for this frame of data on the

encoder input pins. The data is loaded into the MC145532

during one frame, encoded on the next frame, and read dur-

ing the third frame.

ENCODER OUTPUT — LONG FRAME

Figure 4 shows the timing of the encoder output in long

frame mode. The enable must be wider than two falling

edges of the EDC to be in long frame mode. If the enable falls

before the correct number of bits have been presented to the

output (EDO), the transcoder will complete the presentation

of the bits to the output with the LSB being one half of an

EDC period wide. If the enable falls after the one half EDC

period of the LSB, then the LSB will be extended up to the full

EDC clock period and the subsequent data will be a recircu-

lation of the previous data, which repeats until the enable pin

falls. This is shown on the second enable for the 16 kbps en-

coding rate example in Figure 4.

DECODER INPUT — SHORT FRAME

Figure 5 shows the timing of the decoder data clock, the

decoder input enable, and the decoder data input pins in

short frame operation. Note that in this mode only a 32 kbps

decoding rate can be selected.

DECODER INPUT — LONG FRAME

Figure 6 shows the clock, enable, and data signals for the

decoder input in long frame mode.

The determination of the decoding rate is made based on

the number of falling DDC edges seen by the MC145532

while DIE is high. Four edges implies a 32 kbps decoding

rate, three edges implies a 24 kbps decoding rate, two edges

implies a 16 kbps rate, and from five to eight edges inclusive

imply a 64 kbps rate. The decoding rate may be changed on

a frame–by–frame basis.

MOTOROLA

MC145532

3

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