MEJ02C2016_M5M5J167KT Ver la hoja de datos (PDF) - Hitachi -> Renesas Electronics
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MEJ02C2016_M5M5J167KT
Hitachi -> Renesas Electronics
MEJ02C2016_M5M5J167KT Datasheet PDF : 11 Pages
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Jan.10,2003 Ver. 2.1
M5M5J167KT - 70HI
MITSUBISHI LSIs
16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle( W# control mode )
A 0~19
(Word Mode)
A -1~19
(Byte Mode)
BC1#,
BC2#
(Note5)
S1#
(Note5)
S2
(Note5)
tCW
tsu (BC1) or tsu(BC2)
tsu (S1)
tsu (S2)
(Note5)
(Note5)
(Note5)
OE#
tsu (A)
W#
DQ1~16
(Word Mode)
DQ1~8
(Byte Mode)
tdis(OE)
Write cycle (BC# control mode)
A 0~19
(Word Mode)
A -1~19
(Byte Mode)
BC1#,
tsu (A)
BC2#
tsu (A-WH)
tw (W)
tdis (W)
DATA IN
STABLE
tsu (D) th (D)
tCW
trec (W)
ten(OE)
ten (W)
tsu (BC1) or
tsu (BC2)
trec (W)
S1#
(Note5)
(Note5)
S2
(Note5)
(Note7)
(Note5)
W#
DQ1~16
(Word Mode)
DQ1~8
(Byte Mode)
(Note5)
(Note6)
tsu (D)
th (D)
DATA IN
STABLE
(Note5)
Note 5: Hatching indicates the state is "don't care".
Note 6: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low.
Note 7: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of
S1# or rising edge of S2, the outputs are maintained in the high impedance state.
Note 8: Don't apply inv erted phase signal externally when DQ pin is in output mode.
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