MIC1832 Ver la hoja de datos (PDF) - Micrel
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MIC1832 Datasheet PDF : 7 Pages
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MIC1832
Pin Configuration
PBRST 1
TD 2
TOL 3
GND 4
MIC1832
8 VCC
7 ST
6 RST
5 RST
8-Pin PDIP Package
8-Pin SOIC Package
Micrel, Inc.
Pin Description
Pin Number
1
2
3
4
5
6
7
8
Pin Name
/PBRST
TD
TOL
GND
RST
/RST
/ST
VCC
Pin Function
Pushbutton Reset Input: This input is debounced and can be driven with ex-
ternal logic signals or by means of a mechanical pushbutton to actively force
a reset. All pulses less than 1ms in duration on the /PBRST pin are ignored,
whereas, any pulse with a duration of 20ms or greater is guaranteed to
cause a reset.
Time Delay input: This input selects the timebase used by the watchdog
timer. When TD = 0V, the watchdog timeout period is set to a normal value
of 150ms, when TD = open, the watchdog timeout period is et to a nominal
value of 600ms and when TD = VCC, the watchdog period is 1.2s nominally.
Tolerance Select Input: Selects whether 5% or 10% of VCC is used as the
reset threshold voltage. When TOL = 0V, the 5% tolerance level is selected
and when TOL = VCC, a 10% tolerance level is selected.
IC ground pin, 0V reference
RST is asserted high if either VCC goes below the reset threshold, the watch-
dog times out or /PBRST is pulled low for a minimum of 20ms. RST remains
asserted for one reset timeout period after VCC exceeds the reset threshold
or after the watch times out or after /PBRST goes high.
/RST is asserted low if either VCC goes below the reset threshold, the watch-
dog times out or /PBRST is pulled low for a minimum of 20ms. /RST remains
asserted for one reset timeout period after VCC exceeds the reset threshold
or after the watch times out or after /PBRST goes high. Open-drain output
Input to watchdog timer. If /ST does not see a transition from high to low
within the watchdog timeout period, RST and /RST will be asserted.
Primary supply input, +5V
MIC1832
2
January 2006
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