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MK2049-02

Communications Clock PLLs

Integrated Circuit Systems 

MK2049-02/03

Communications Clock PLLs

LAYOUT AND EXTERNAL COMPONENTS (continued)

Crystal Specifications

Parameter

Operating Temperature Range

Initial Accuracy at 25 C

Temperature stability

Aging, first year

Aging, 10 years

Load Capacitance

Shunt Capacitance, C0

Motional Capacitance, C1

C0/C1 ratio

Equivalent Series Resistance

Minimum

0

-20

-30

-5

-20

none

*This ratio decreases for lower crystal frequencies.

Typical

25

Note 1

Maximum

70

20

30

5

20

7

none

250

35

Units

C

ppm

ppm

ppm

ppm

pF

pF

none

Ohms

Note 1: Nominal crystal load capacitance specification varies with frequency.

Contact the ICS MicroClock applications department at (408)297-1201.

Note 2: The third overtone mode of the crystal and all spurs must be >200 ppm

away from 3x the fundamental resonance shown in the table below.

For recommended crystal devices, please contact the ICS MicroClock application department

at 408-297-1201.

MDS 2049-02/03 B

10

Revision 040601

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

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