MK2049-34A Ver la hoja de datos (PDF) - Integrated Circuit Systems
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MK2049-34A Datasheet PDF : 8 Pages
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MK2049-34A
3.3 Volt Communications Clock VCXO PLL
Pin Assignment
FS1 1
X2 2
X1 3
VDD 4
FCAP 5
VDD 6
GND 7
CLK 8
CLK/2 9
8k 10
20 FS0
19 RES
18 CAP2
17 GND
16 CAP1
15 VDD
14 GND
13 ICLK
12 FS3
11 FS2
20-pin (300) mil SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RES
FS0
Pin
Type
Input
XO
XI
Power
-
Power
Power
Output
Output
Output
Input
Input
Input
Power
Power
Loop
Filter
Power
Loop
-
Input
Pin Description
Frequency select 1. Determines CLK input/outputs per table on page 3.
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
Power supply. Connect to +3.3 V.
Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
Power supply. Connect to +3.3 V.
Connect to ground
Clock output determined by status of FS3:0 per tables on page 3.
Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of
CLK.
Recovered 8 kHz clock output.
Frequency select 2. Determines CLK input/outputs per tables on page 3.
Frequency select 3. Determines CLK input/outputs per tables on page 3.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Power Supply. Connect to +3.3 V.
Connect the loop filter ceramic capacitors and resistor between this pin and
CAP2.
Connect to ground.
Connect the loop filter ceramic capacitors and resistor between this pin and
Connect a 10-200kΩ resistor to ground. Contact ICS at telecom@icst.com for
recommended value for your application.
Frequency select 0. Determines CLK input/outputs per table on page 3.
MDS 2049-34A A
2
Revision 032504
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
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