MK2049-34A Ver la hoja de datos (PDF) - Integrated Circuit Systems
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MK2049-34A Datasheet PDF : 8 Pages
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MK2049-34A
3.3 Volt Communications Clock VCXO PLL
PC Board Layout
A proper board layout is critical to the successful use of the MK2049-34A. In particular, the CAP1 and CAP2 pins
are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible
and the two capacitors and resistor must be mounted next to the device as shown below. The capacitor shown
between pins 15 and 17, and the one between pins 4 and 7 are the power supply decoupling capacitors. The high
frequency output clocks on pins 8 and 9 should have a series termination of 33Ω connected close to the pin.
Additional improvements will come from keeping all components on the same side of the board, minimizing vias
through other signal layers, and routing other signals away from the MK2049. You may also refer to application note
MAN05 for additional suggestions on layout of the crystal selection.
The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the
stray capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is
accurate to much less than 1 ppm, so the MK2049-34A may lock and run properly even if the board capacitance is
not adjusted with these fixed capacitors. However, ICS recommends that the adjustment capacitors be included to
minimize the effects of variation in individual crystals, temperature, and aging. The value of these capacitors
(typically 0 - 4 pF) is determined once for a given board layout, using the procedure found in application note
MAN05 (http://www.icst.com/products/summary/man05.htm).
Optional -
cap
see text G
V
resist
resist
Cutout in ground and power plane.
Route all traces away from this area.
1
20
2
19
resist
G
3
18
resist
4
17
G
5
16
cap
6
15
V
7
14
8
13
9
12
V = connect to VDD
10
11
G = connect to GND
Figure 2. Typical MK2049-34 Layout
MDS 2049-34A A
5
Revision 032504
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
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