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ML7022-01

Single Rail Dual Channel PCM CODEC

Oki Electric Industry 

1Semiconductor

FEDL7022-01-06

ML7022-01

TIMING DIAGRAM

MCK

BCLK

TXS

XSYNC

DOUT

TXD1

TMB

1

2

3

4

5

6

7

8

TSX

TTSDWS

TXD2

MSD D2

D3

D4

D5

D6

D7

D8

MCK

BCLK

TRS

RSYNC

DIN

Figure 1 Transmit Side Timing Diagram

TMB

1

2

3

4

5

6

7

8

TSR

TWS TDS

TDH

MSD D2

D3

D4

D5

D6

D7

D8

Figure 2 Receive Side Timing Diagram

1

9

17

25

1

BCLK

XSYNC

DOUT

CH1 PCM DATA ECHO bits

CH2 PCM DATA ECHO bits

Figure 3 Transmit Side Bit Configuration

1

9

17

25

1

BCLK

RSYNC

DIN

CH1 PCM DATA Latch Data CH2 PCM DATA Latch Data

CH1 power down control bit

CH2 power down control bit

Figure 4 Receive Side Bit Configuration

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