¡ Semiconductor
TIMING DIAGRAM
MSM7557
ST
SD
RT
FD,RD
FDE
RT
Internal RD
FD
RD
50%
50%
tS
tH
Figure 1 Input Data Timing
50%
50%
tD
Figure 2 Output Data Timing
N-2 N-1
N
D1
D2
D3
D1
D2
D3
N-2, N-1, N : Frame shnchronous signal
Figure 3 Receive Signal Timing
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