MSM7583 Ver la hoja de datos (PDF) - Oki Electric Industry

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MSM7583

π/4 Shift QPSK MODEM

Oki Electric Industry 

¡ Semiconductor

MSM7583

RXD1, RXC1, RXSC1

Channel 1 receive data, receive clock, and receive symbol clock output pins.

During power-on, these output pins are at the output level of the clock recovery circuit selected

by a combination of SLS11 and SLS21 (described later). (Refer to Fig. 3.)

RXD2, RXC2, RXSC2

Channel 2 receive data, receive clock, and receive symbol clock output pins.

During power-on, these output pins are at the output level of the clock recovery circuit selected

by a combination of SLS12 and SLS22 (described later). (Refer to Fig. 3.)

SLS11, SLS21, SLS12, SLS22

Receiver slot select signal pins of Channel 1 (SLS11, SLS21) and Channel 2 (SLS12, SLS22).

The MSM7583 has four sets of clock recovery circuits and four AFC information storage

registers. One of the sets is selected according to a combination of the signals at these pins.

(Refer to Fig. 3.)

Channel 1 (SLS21, SLS11) = (0, 0): Slot 1, (0, 1): Slot 2

(1, 0): Slot 3, (1, 1): Slot 4

Channel 2 (SLS22, SLS12) = (0, 0): Slot 1, (0, 1): Slot 2

(1, 0): Slot 3, (1, 1): Slot 4

RXD1 (RXD2)

RXC1 (RXC2)

RXSC1 (RXSC2)

SLS21 (SLS22)

SLS11 (SLS12)

The recovery data and clock pulse are

selected asynchronously by the SLS signals.

Figure 3 RXD, RXC, and RXSC Timing Diagram

RXD0, RXC0, RXSC0

Receive data, receive clock, and receive symbol clock outputs.

These pins are at the output level selected by RXSEL (described below).

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