MX98715 Ver la hoja de datos (PDF) - Macronix International

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MX98715

SINGLE CHIP FAST ETHERNET NIC CONTROLLER - CRYSTAL VERSION

Macronix International 

MX98715AEC-C

bit 24:Data parity Report, is set to 1 only if PERR# active and PFCS<6> is also set.

bit 26-25:Device Select Timing of DEVSELB pin.

bit 27:not used

bit 28:Receive Target Abort, is set to indicate a transaction is terminated by a target abort.

bit 29:Receive Master Abort, is set to indicate a master transaction with Master abort.

bit 30:Signal System Error, is set to indicate assertion of SERR#.

bit 31:Detected Parity Error, is set whenever a parity error detected regardless of PFCS<6>.

5.1.3 PCI REVISION REGISTER ( PFRV ) ( Offset 0Bh-08h )

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Base Class

Subclass

Revision Number

Step Number

bit 3 - 0 : Step Number= 5h ( Previous MX98715 = 0h ).

bit 7 - 4 : Revision Number, fixed to 2h for MX98715AEC-C

( Previous MX98715A series is also fixed to 2h )

bit 15 - 8 : not used

bit 23 - 16 : Subclass, fixed to 0h.

bit 31 - 24 : Base Class, fixed to 2h.

5.1.4 PCI LATENCY TIMER REGISTER ( PFLT ) (Offset 0Fh-0Ch)

PFLT Register (0Fh-0Ch)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Configuration Latency Timer

System cache line size

bit 0 - bit 7 : System cache line size in units of 32 bit word, device driver should use this value to program CSR0<15:14>.

bit 8 - bit 15 : Configuration Latency Timer, when MX98715AEC-C assert FRAME#, it enables its latency timer to

count.

If MX98715AEC-C deasserts FRAME# prior to timer expiration, then timer is ignored. Otherwise, after timer expires,

MX98715AEC-C initiates transaction termination as soon as its GNT# is deasserted.

P/N:PM0655

REV. 0.3, MAY. 04, 2000

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