MX98715 Ver la hoja de datos (PDF) - Macronix International

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MX98715

SINGLE CHIP FAST ETHERNET NIC CONTROLLER - CRYSTAL VERSION

Macronix International 

MX98715AEC-C

5.1.13 PCI POWER MANAGEMENT COMMAND AND STATUS REGISTER ( PPMCSR ) ( 4Bh-48h )

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000 00 0

Data

Bridge Extension Support

PME_Status

Data_Scale

Data_Select

PME_EN

Reserved

Power State

bit 1-0 : Power_State, read/write, D0 mode is 00, D1 mode is 01, D2 mode is 10, D3 hot mode is 11.

bit7-2 : all 0. Reserved.

bit8 : PME_EN, set 1 to enable LANWAKE. Set 0 to disable LANWAKE assertion.

bit 12-9 : Data_Select for report in the Data register located at bit 31:24.

bit 14-13 : Data_Scale, read only.

bit 15 : PME_Status independent of the state of PME_EN.

When set, indicates a assertion of LANWAKE pin. (support D3 cold).

Write 1 to clear the LANWAKE signal. Write 0, no effect.

bit 21-16 : Reserved.

bit 22 : B2_B3#, B2_B3 support for D3 hot, meaningful only if BPCC_EN = 1, read only.

bit 23 : BPCC_EN, Bus Power/Clock Control Enable, read only.

bit 31-24 : Data, read only.

P/N:PM0655

REV. 0.3, MAY. 04, 2000

11

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