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MX98715A

SINGLE CHIP FAST ETHERNET NIC CONTROLLER

Macronix International 

MX98715A

5.1.11 PCI DRIVER AREA REGISTER ( PFDA ) ( 43h-40h )

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Sleep Type

Board Type

Driver Special Use

bit 31 : Sleep Mode, set to sleep mode which allows access to PCI configuration space, a hardware reset or reset to

this bit can exit from sleep mode. Magic packet can be received under sleep mode if CSR<22> (Magic Packet

Enable) is set.

bit 30 : not used

bit 29 : board type

bit 15 - 8 : driver is free to read and write this field for any purpose.

bit 7 - 0 : not used.

5.1.12 PCI POWER MANAGEMENT CAPABILITY REGISTER ( PPMC ) ( 47h-44h )

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000 00 00 0

PME_Support

D2_Support

D1_Support

AUX_I

DSI

Auxiliary Power Source

PME Clock

Version

Next Pointer

Capability ID

bit 31- 27 : PME_Support, read only indicates the power states in which the function may assert LANWAKE pin.

bit 31 ---- PME_D3cold (value=1)

bit 30 ---- PME_D3warm (value=1)

bit 29 ---- PME_D2 (value=1)

bit 28 ---- PME_D1 (value=1)

bit 27 ---- PME_D0 (value=1)

bit 26 : D2 mode support, read only, set to 1.

bit 25 : D1 mode support, read only, set to 1.

bit 24-22 : AUX_I bits. Auxiliary current field, set to 100.

bit 21 : DSI, read only, set to 0.

bit 20 : Auxiliary power source, set to 1. This bit only valid when bit 15 is a '1'.

bit 19 : PME Clock, read only, set to 0.

bit 18-16 : PCI power management version, set to 001, read only.

bit 15-8 : Next Pointer, all bits set to 0.

bit 7-0 : Capability ID, read only, a 1 indicates that the data structure currently being pointed to is the PCI power

managment data structure.

P/N:PM0537

REV. 1.2, FEB. 24, 1999

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