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MX98715A

SINGLE CHIP FAST ETHERNET NIC CONTROLLER

Macronix International 

MX98715A

4. PIN DESCRIPTION ( 128 PIN PQFP )

( T/S : tri-state, S/T/S : sustended tri-state, I : input, O : output, O/D : open drain )

Pin Name Type

AD[31:0] T/S

CBE[3:0] T/S

Pin No

116, 117

119,120,

122,124,

125,127,

3,4,6,7,9,

10,12,13,

26,28,29,

31-33,35,

36,38,39,

41,42,44,

45,47,48

128,14

25,37

FRAMEB S/T/S 15

TRDYB S/T/S 18

IRDYB S/T/S 17

DEVSELB S/T/S 19

IDSEL I

1

PCICLK I

113

RSTB

I

112

LANWAKE O

110

INTAB

SERRB

O/D 111

O/D 23

PERRB S/T/S 22

P/N:PM0537

128 Pin Function and Driver

PCI address/data bus: shared PCI address/data bus lines. Little or big endian

byte ordering are supported.

PCI command and byte enable bus: shared PCI command byte enable bus,

during the address phase of the transaction, these four bits provide the bus

command. During the data phase, these four bits provide the byte enable.

PCI FRAMEB signal: shared PCI cycle start signal, asserted to indicate the

beginning of a bus transaction. As long as FRAMEB is asserted, data

transfers continue.

PCI Target ready: issued by the target agent, a data phase is completed on

the rising edge of PCICLK when both IRDYB and TRDYB are asserted.

PCI Master ready: indicates the bus master's ability to complete the current

data phase of the transaction. A data phase is completed on any rising edge

of PCICLK when both IRDYB and TRDYB are asserted.

PCI slave device select: asserted by the target of the current bus access.

When 98715A is the initiator of current bus access, the target must assert

DEVSELB within 5 bus cycles, otherwise cycle is aborted.

PCI initialization device select: target specific device select signal for

configuration cycles issued by host.

PCI bus clock input: PCI bus clock range from 16MHz to 33MHz.

PCI bus reset: host system hardware reset.

Power Management Event:When high indicating a power management event

occures, such as detection of a Magic packet, a wake up frame, or link change.

PCI bus interrupt request signal: wired to INTAB line.

PCI bus system error signal: If an address parity error is detected and CFCS

bit 8 is enabled, SERRB and CFCS's bit 30 will be asserted.

PCI bus data error signal: As a bus master, when a data parity error is

detected and CFCS bit 8 is enabled, CFCS bit 24 and CSR5 bit 13 will be

asserted. As a bus target, a data parity error will cause PERRB to be

asserted.

REV. 1.2, FEB. 24, 1999

3

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