MX98715AEC-D Ver la hoja de datos (PDF) - Macronix International
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MX98715AEC-D Datasheet PDF : 40 Pages
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MX98715AEC-D
5. 2.1 BUS MODE REGISTER ( CSR0 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIE-Write and Invalidate Enable
RLE-Read Line Enable
RME-Read Multiple Enable
TAP-Transmit Automatic Polling
ZERO-Must be zero
CAL-Cache Alignment
PBL-Programmable Burst Length
BLE-Big/Little Endian
DSL-Descriptor Skip Length
BAR0-Bus Arbitration bit 0
SWR-Software Reset
Field
0
Name
SWR
1
BAR0
6:2
DSL
7
BLE
13:8 PBL
15:14 CAL
18:17 TAP
21
RME
23
RLE
24
WLE
Description
Software Reset, when set, MX98715AEC-D resets all internal hardware with the exception
of the configuration area and port selection.
Internal bus arbitration scheme between receive and transmit processes.
The receive channel usually has higher priority over transmit channel when receive FIFO
is partially full to a threshold. This threshold can be selected by programming this bit. Set
for lower threshold, reset for normal threshold.
Descriptor Skip Length, specifies the number of longwords to skip between two descrip-
tors.
Big/Little Ending, set for big endian byte ordering mode, reset for little endian byte ordering
mode, this option only applies to data buffers
Programmable Burst Length, specifies the maximum number of longwords to be trans-
ferred in one DMA transaction. default is 0 which means unlimited burst length, possible
values can be 1,2,4,8,16,32 and unlimited .
Cache Alignment, programmable address boundaries of data burst stop, MX98715AEC-D
can handle non-cache- aligned fragment as well as cache-aligned fragment efficiently.
Transmit Auto-Polling time interval, defines the time interval for MX98715AEC-D to per-
forms transmit poll command automatically at transmit suspended state.
PCI Memory Read Multiple command enable, indicates bus master may intend to fetch
more than one cache lines disconnecting.
PCI Memory Read Line command enable, indicating bus master intends to fetch a com-
plete cache line.
PCI Memory Write and Invalidate command enable, guarantees a minimum transfer of one
complete cache.
P/N:PM0719
REV. 0.1, FEB. 05, 2001
14
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