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MX98715AEC-D

SINGLE CHIP FAST ETHERNET NIC CONTROLLER

Macronix International 

MX98715AEC-D

TABLE 5.2.1 FATAL BUS ERROR BITS

CSR5<25:23>

000

001

010

011

1XX

Process State

parity error for either SERR# or PERR#, cleared by software reset.

master abort

target abort

reserved

reserved

TABLE 5.2.2 TRANSMIT PROCESS STATE

CSR5<22:20>

000

001

010

011

100

101

110

111

Process State

Stopped- reset or transmit jabber expired.

Fetching transmit descriptor

Waiting for end of transmission

filling transmit FIFO

reserved

Setup packet

Suspended, either FIFO underflow or unavailable transmit descriptor

closing transmit descriptor

TABLE 5.2.3 RECEIVE PROCESS STATE

CSR5<19:17>

000

010

011

100

101

110

111

Process State

Stopped- reset or stop receive command. Fetching receive descriptor

checking for end of receive packet

Waiting for receive packet

Suspended, receive buffer unavailable

closing receive descriptor

Purging the current frame from the receive FIFO due to unavailable receive buffer

queuing the receive frame from the receive FIFO into host receive buffer

P/N:PM0719

REV. 0.1, FEB. 05, 2001

19

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