SPT5220 Ver la hoja de datos (PDF) - Signal Processing Technologies
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SPT5220 Datasheet PDF : 8 Pages
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CIRCUIT DESCRIPTION AND OPERATION
The SPT5220 contains a 10-bit DAC, input buffers and
latches, internally or externally generated voltage refer-
ence and complete video controls. The following describes
the main operation of the device and outlines several
considerations that should be noted to achieve the best
performance.
Figure 1: Timing Waveform7,8,9
tCLK
tPWH
tPWL
CLOCK INPUT
CLK is the device clock input and is typically the pixel clock rate
of the system. It is TTL compatible. The digital data D0-D9 and
all video controls (SYNC, BLANK, BRIGHT) are all latched on
the rising edge of CLK. See figure 1.
CLK
DØ~D9 N-1
Output
Data
tS
tH
N+1
tD
Pipeline Delay
tSET
Note: 7. Output delay (td) is measured from the 50% point of the rising edge of CLK to the full scale transition.
8. Settling time (tset) is measured from the 50% point of full scale transition to the output remaining within ±1, ±2
LSB.
9. Output rise/fall time (tr, tf ) is measured between the 10% and 90% points of full scale transition.
DIGITAL INPUTS AND VIDEO CONTROLS
All ten bits of data (D0-D9, D0 is the LSB) are latched into
the device on the rising edge of each clock cycle. There are
also three video control inputs to generate composite
video outputs. They are SYNC, BLANK and BRIGHT.
A logic 1 on the SYNC input generates the sync level. A logic 1
on the BLANK input generates the pedestal level. BRIGHT is the
bright signal input. These inputs are pipelined to maintain
synchronization with the digital input data. These video controls
produce the output levels needed to be compatible with video
system standards. Table I shows the video control effects on the
analog output.
Table I - Video Output Truth Table
Sync
1
0
0
0
0
0
Blank
X
1
0
0
0
0
Bright
X
X
0
0
1
1
Data (D9-D0)
X
X
000…
111…
000…
111…
IOUT (mA)
0
7.62
9.05
28.10
10.95
30.00
VOUT (V)
0
0.286
0.340
1.054
0.410
1.125
Out (IRE)
-40
0
7.5
100
17.5
110
Description
Sync Level
Blank Level
Black Level
White Level
Enhanced Black Level
Enhanced White Level
Note: 10. Double-terminated load of 75 Ω. VREF=1.235 V RSET=165 Ω. Inverse = 0. N2C = 1.
SPT
4
SPT5220
12/30/98
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