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SPT5220 Ver la hoja de datos (PDF) - Signal Processing Technologies

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componentes Descripción
Lista de partido
SPT5220
SPT
Signal Processing Technologies SPT
SPT5220 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
PC BOARD CONSIDERATIONS
DIGITAL SIGNAL INTERCONNECT
LAYOUT CONSIDERATIONS
To minimize noise on the power lines and ground lines, shield
and decouple the digital inputs. Keep the trace length be-
tween groups of VDD (AVDD, DVDD) and VSS (AVSS, DVSS)
as short as possible to minimize inductive ringing.
SUPPLY AND GROUND CONSIDERATIONS
Use a 0.1 µF ceramic capacitor in parallel with a 10 µF
tantalum capacitor for decoupling between the power line
and the ground line. The digital power plane (DVDD) and the
analog power plane (AVDD) are connected through a ferrite
bead. The digital ground plane (DVSS) and the analog
ground plane (AVSS) are also connected through a ferrite
bead. (See figures 3 and 4). Locate these ferrite beads within
three inches of the SPT5220.
The PCB line between the TTL driver (that drives the SPT5220)
and the input to the SPT5220 will have a low impedance
source and be terminated with a high impedance. It behaves
like a low impedance transmission line so signal transitions
will be reflected from the high impedance input of the SPT5220.
To reduce ringing caused by transmission line mismatch,
shorten the line length or terminate the line. Both serial and
parallel termination methods will work, but serial is preferred.
Serial termination is achieved by installing a resistor of
approximately 50 between the TTL driver output and the
SPT5220 digital input.
ANALOG SIGNAL INTERCONNECT
To minimize noise pickup and reflections due to impedance
mismatch, locate the SPT5220 as closely as possible to the
output connector. The line between the DAC output and the
monitor input should be regarded as a transmission line since
it can cause problems in transmission line mismatch. Use the
double-termination method to avoid these problems. By
using the double terminated method, the transmission lines
are matched, providing an ideal, nonreflective system.
28
1
A
B
C
SPT
28-LEAD PLASTIC DIP (PDIP) PACKAGE OUTLINE
J
D
INCHES
MILLIMETERS
K
SYMBOL MIN
MAX
MIN
MAX
A
0.198 typ
5.08 typ
B
0.117
0.140
3.00
3.60
C
0.014
0.022
0.36
0.56
D
0.099 typ
2.54 typ
E
0.055
0.063
1.42
1.62
F
0.008
0.014
0.20
0.35
I
G
0.142
0.158
3.65
4.05
H
0.000
0.594
15.24
I
0.523
0.538
13.40
13.80
J
1.439
1.455
36.90
37.30
K
0 .080 typ
2.04 typ
L
0°
15°
H
F
G
L
E
SPT5220
7
12/30/98

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