Philips Semiconductors
FLEX™ Pager Decoder
Product specification
PCD5008
8.4.3 CONFIGURATION SEQUENCE
A typical configuration and synchronisation sequence
would be as follows, see Fig.11 for event timings:
1. The PCD5008 is reset by the host.
2. After 1 second the PCD5008 interrupts the host to
read the part ID by pulling the READY line LOW.
3. The host pulls SS LOW at the start of each
SPI transfer and clocks out the part ID data.
4. The host configures the following aspects of PCD5008
operation:
a) General configuration (Section 8.4.4)
b) Receiver operation (Section 8.5)
c) FLEX™ CAPCODE configuration (Section 8.6).
The PCD5008 writes a part ID packet in response to
each incoming packet.
5. At the end of each packet the PCD5008 pulls the
READY line HIGH, and then LOW again to indicate
that packet processing is complete.
6. The host writes a control packet to enable FLEX™
decoding in the PCD5008 (Section 8.4.7).
7. The host writes a checksum packet to enable SPI data
output by the PCD5008 (Section 8.4.2).
8. On recognising a SYNC word, the PCD5008
synchronises to the channel.
9. The PCD5008 initiates an SPI transfer writing the
status packet, indicating that it is now in synchronous
mode.
handbook, full pagewidth
SPI
HOST-TO-DECODER
SPI
DECODER-TO-HOST
RESET
READY
(1)
(2)
configuration packets
(addresses, receiver etc.) control packet (6)
checksum packet (7)
partid packet (4)
status packet (9)
(5)
(5)
(5)
partid packet (4)
SS
(3)
FLEX DATASTREAM
(8)
SYNC
MBK097
Numbers within parenthesis refer to sequence numbers, see Section 8.4.3.
Fig.11 Typical configuration and synchronisation sequence.
1998 Jun 17
16