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PCD5008

FLEX™ Pager Decoder

Philips Electronics 

Philips Semiconductors

FLEX™ Pager Decoder

Product specification

PCD5008

The PCD5008 interfaces to a host through a serial

peripheral interface (SPI). The host can then interpret the

message information in an appropriate manner (numeric,

alphanumeric, binary, etc.). This function is provided by

the FLEXstack™ software.

The PCD5008 enables the host to operate in a low power

mode when no message information for the paging device

is being received. It has a 38.4 kHz clock output capable

of driving other devices, and has a 1-minute timer that

offers low-power support for a real-time clock function on

the host. The host can use receiver control lines which are

not required by the receiver as expansion ports to control

other peripheral devices.

8.2 Clocking, reset and start-up

8.2.1 OSCILLATOR

The PCD5008 uses an inverting crystal oscillator.

The clock signal for the internal circuitry is derived via an

amplifier from the oscillator input pin EXTAL. Alternatively,

an external clock signal can be fed in at input pin EXTAL.

In this case the internal oscillator can be disabled by

pulling the OSCPD input pin HIGH.This reduces current

consumption and routes EXTAL directly to the internal

clock signal. When using a crystal, an external feedback

resistor and the load capacitances need to be connected

to pins EXTAL and XTAL (Fig.18). See Section 12 for the

recommended crystal parameters and the specification of

the oscillator transconductance to guarantee correct

start-up.

8.2.2 RESET AND START-UP CONDITIONS

The PCD5008 is reset by pulling the RESET input LOW.

After releasing the RESET by pulling it HIGH, the

PCD5008 counts 76800 clock cycles (typically 1 second)

before pulling READY LOW to indicate that the decoder is

ready for configuration via the SPI.

See Fig.3 and Section 11 for the PCD5008 timing

specifications when power is applied.

See Fig.4 and Section 11 for the PCD5008 timing

specifications when it is reset.

handbook, full pagewidth

VDD

oscillator

RESET

READY

tstrt(osc)

th(rst)

tWUL(osc-READY)

tHL(RESET-READY)

Fig.3 Start-up timing.

MBK031

1998 Jun 17

7

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