PCD5008 Ver la hoja de datos (PDF) - Philips Electronics

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PCD5008

FLEX™ Pager Decoder

Philips Electronics 

Philips Semiconductors

FLEX™ Pager Decoder

Product specification

PCD5008

handbook, full pagewidth

RESET

READY

tW(rst)

tLH(RESET-READY)

tHL(RESET-READY)

MBK033

Fig.4 Reset timing.

8.3 Serial peripheral interface (SPI)

8.3.1 GENERAL

All data communication between the PCD5008 and the

host is done via the SPI using 32-bit data packets at data

rates up to 1 Mbits/s. SPI transfers are full-duplex and can

be initiated by either the host which acts as the SPI master

providing the data clock for packet transfer, or the

PCD5008 as an SPI slave.

The host can send packets to configure or control the

PCD5008 or a checksum packet to validate SPI

communication (Section 8.4.2). The PCD5008 buffers

data packets, relating to received data, into a 32 packet

transmit buffer. The PCD5008 can send either a status

packet, a part ID packet, or packets from the transmit

buffer. In the event of a buffer overflow, the PCD5008

stops decoding and clears the transmit buffer.

8.3.2 SPI INTERCONNECT

Connection on the PCD5008 consists of a READY pin and

4 SPI pins (SS, SCK, MOSI and MISO):

READY: output signal; indicates that data is available

from the PCD5008

SS: SPI select; used as PCD5008 chip select

SCK: serial clock; output from the host used for clocking

data

MOSI: master output slave input; data output from the

host

MISO: master input slave output; data output from the

PCD5008.

1998 Jun 17

8

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