PCK2022RADGG Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Lista de partido
PCK2022RADGG
Philips Electronics
PCK2022RADGG Datasheet PDF : 14 Pages
| |||
Philips Semiconductors
CK00 (100/133 MHz) spread spectrum differential
system clock generator
Product data
PCK2022RA
PIN DESCRIPTION
PIN(S)
SYMBOL
1
IOCLK
3, 4
48M_0/SELA
48M_1/SELB
7, 8
HCLK0
HCLKB0
10, 11
HCLK1
HCLKB1
13, 14
HCLK2
HCLKB2
16, 17
HCLK3
HCLKB3
42, 21
HCLK4
HCLKB4
39, 38
HCLK5
HCLKB5
36, 35
HCLK6
HCLKB6
33, 32
HCLK7
HCLKB7
19
REFCLK/SELC
20
SPREAD
21
XIN
22
XOUT
26
IREF
29, 30
44
48
2, 6, 12,
18, 24, 31,
37, 43
5, 9, 15,
21, 28, 34,
40, 47
25, 46
27, 45
MULTSEL0
MULTSEL1
PWRDWN
SEL100/133
VDD3
GND
AVDD
AGND
FUNCTION
Dual frequency pin which can operate at either 33 MHz or 66 MHz per the selection table.
3.3 V fixed 48 MHz clock outputs. During power-up pins function as latched inputs that enable SELA and
SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in.
Host output pair 0
Host output pair 1
Host output pair 2
Host output pair 3
Host output pair 4
Host output pair 5
Host output pair 6
Host output pair 7
3.3 V fixed 14.318 MHz output. During power-up, pin functions as a latched input that enables SELC prior
to the pin being used for the clock output. Part must be clocked to latch data in.
Enables spread spectrum mode when held LOW on differential host outputs and 33 MHz IOCLK clocks.
Asserts LOW.
Crystal input
Crystal output
This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the correct current.
Select input pin used to control the scaling of the HCLK and HCLKB output current.
Device enters power-down mode when held LOW. Asserts LOW.
Select input pin for enabling 133 MHz or 100 MHz CPU outputs
3.3 V power supply
Ground
3.3 V power supply for analog circuits
Ground for analog circuits
2003 Jul 31
3
Share Link: