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PE42672 Datasheet PDF : 4 Pages
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PE42672
Advance Information
Table 4. Pin Descriptions
Pin No.
1
26
35
46
55
65
75
85
9
10
115
12
13
145
155
166
175
186
195
206
215
226
Pin Name
ANT
TX1
GND
TX2
GND
TX3
GND
GND
VDD
V3
GND
V2
V1
GND
GND
RX4
GND
RX3
GND
RX2
GND
RX1
Description
RF Common – Antenna
RF I/O - TX1
Ground (Requires two bond wires)
RF I/O – TX2
Ground
RF I/O – TX3
Ground
Ground
Supply
Switch control input, CMOS logic level
Ground
Switch control input, CMOS logic level
Switch control input, CMOS logic level
Ground
Ground
RF I/O – RX4
Ground
RF I/O – RX3
Ground
RF I/O – RX2
Ground
RF I/O – RX1
Notes: 5. Bond wires should be physically short and connected to
ground plane for best performance.
6. Blocking capacitors needed only when non-zero DC
voltage present.
Figure 3. Pad Configuration (Top View)
TX1 2
GND 3
TX2 4
GND 5
TX3 6
GND 7
1
PE42672
Die
22 RX1
21 GND
20 RX2
19 GND
18 RX3
17 GND
16 RX4
15 GND
GND 86
9
10 11 12 13 14
Table 5. Truth Table
Path
RX1 - ANT
RX2 - ANT
RX3 - ANT
RX4 - ANT
TX1 - ANT
TX2 - ANT
TX3 - ANT
All Off
V1
V2
V3
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 6. Ordering Information
Order Code
42672-90
42672-99
42672-00
Description
PE42672-DIE-D
PE42672-DIE-400G
PE42672-DIE-1H
Package
Film Frame
Waffle Pack
Evaluation Kit
Shipping Method
Wafer (Gross Die / Wafer Quantity)
400 Dice / Waffle Pack
1/ box
Document No. 70-0197-01 │ www.psemi.com
Contact sales@psemi.com for full version of datasheet
©2005 Peregrine Semiconductor Corp. All rights reserved.
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