PEB20954(1999) Ver la hoja de datos (PDF) - Infineon Technologies
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PEB20954 Datasheet PDF : 132 Pages
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PEB 20954
PEF 20954
Introduction
• Support of Channel Associated Signaling (CAS) BR transparency (robbed bits) in
send path
• Selectable µ- to A-Law or A- to µ-Law Conversion on a global or per channel basis
• Configurable idle channel supervision
• Clear channel capability (64 clear) on a per channel basis
• Special evaluation of bit 8 in T1 Modem calls possible (56 clear)
• Serial 256 kbit/s interface to control the functions disable cancelling, freeze
coefficients, clear channel, disable NLP, PCM Law conversion control or
combinations of above
• Monitor pins for several internal states
• Switchable global loop from receive output to send input and send output to receive
input
• Switchable global attenuation (2.5 dB or 6 dB) at the receive and send output
• Flexible Microprocessor Interface (SIEMENS/Intel or Motorola type, Mux and Demux
mode) usable for:
– configuration of parameters such as thresholds and functions on a global basis
– Disable cancelling, freeze coefficients, clear channel, disable NLP, PCM Law
conversion control (all functions individually for each channel)
– support of background tests for disabled or idle timeslots (feeding and reading of
test levels)
– possibility to read levels, attenuations, internal states, signal values or all
coefficients of a selected timeslot
– control of the RAM Built In Self Test
• Advanced Integrated Watchdog Timer
• Supervision of the input clocks
• Various clock modes possible for 32.768 MHz and 8.192 MHz
• Boundary Scan according to IEEE 1149.1 Standard
• Power supply: 3.3 V, 5V tolerant inputs
• Typical power dissipation: 700 - 900 mW
• Plastic package TQFP 144
• Temperature range: -40°C - 85°C
Preliminary Data Sheet
7
04.99
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