PI6C100V Ver la hoja de datos (PDF) - Pericom Semiconductor
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PI6C100V Datasheet PDF : 13 Pages
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PI6C100
Precision Clock Synthesizer
for Desktop PCs
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CPU_STOP# is an input signal used to turn off the CPU clocks
for low power operation. CPU_STOP# is asserted asynchronously
by the external clock control logic with the rising edge of free
running PCI clock and is internally synchronized to the external
PCICLK_F output.
All other clocks continue to run while the CPU clocks are disabled.
The CPU clocks are always stopped in a low state and started
guaranteeing that the high pulse width is a full pulse. CPU clock
on latency is 2 or 3 CPU clocks and CPU clock off latency is 2 or
3 CPU clocks.
Power Management Timing
Signal
Signal State
Latency
No. of rising edges of free running PCICLK
CPU_STOP#
0 (disabled)
1
1 (enabled)
1
PCI_STOP#
0 (disabled)
1
1 (enabled)
1
PWR_DWN# 1 (normal operation)
3ms
0 (power down
2 max.
Notes:
1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs between
when the clock disable goes low/high to when the first valid clock comes out of the device.
2. Power up latency is from when PWR_DWN# goes inactive (high) to when the first valid clocks
are driven from the device.
CPUCLK
(Internal)
CPUCLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
(External)
CPU_STOP# Timing Diagram
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3 CPU_STOP# is an input signal that is made synchronous to the free running PCICLK_F.
4. ON/OFF latency shown is 2 CPU clocks.
201
PS8142A 10/13/98
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