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PI6C100V

Precision Clock Synthesizer for Desktop PC'’s

Pericom Semiconductor 

PI6C100

Precision Clock Synthesizer

for Desktop PC’s 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122

PCI_STOP# is an input signal used to turn off the PCI clocks for low power operation. PCI clocks are stopped in the low state and started

with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic.

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK_F

(Free-running)

CPU_STOP#

PCI_STOP#

PWR_DWN#

PCICLK

(External)

PCI_STOP# Timing Diagram

Notes:

1. All timing is referenced to the CPUCLK.

2. The Internal label means inside the chip and is a reference only.

The PWR_DWN# is used to place the device in a very low power state. PWR_DWN# is an asynchronous active low input. Internal clocks

are stopped after the device is put in power down mode. The power on latency is less than 3ms. PCI_STOP# and CPU_STOP# are “don’t

cares” during the power down operations. The REF0 clock is stopped in the LOW state as soon as possible.

CPUCLK

(Internal)

PCICLK

(Internal)

PWR_DWN#

CPUCLK

(External)

PCICLK

(External)

VCO

Crystal

Notes:

PWR_DWN# Timing Diagram

1. All timing is referenced to the CPUCLK.

2. The Internal label means inside the chip and is a reference only.

3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.

4. The shaded sections on the VCO and the Crystal signals indicate an active clock.

202

PS8142A 10/13/98

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