PI90LVT14 Ver la hoja de datos (PDF) - Pericom Semiconductor
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PI90LVT14 Datasheet PDF : 7 Pages
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PI90LV14/PI90LVT14 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
1:5 Clock Distribution
Features
Meets and Exceeds the Requirements of ANSI
TIA/EIA-644-1995
Designed for clocking rates up to 320MHz
Operates from a single 3.3V Supply
Low Voltage Differential Signaling (LVDS) with Output
Voltages of ±350mV into a 100-ohm load
Choice between LVDS or TTL clock input
Synchronous Enable/Disable
Clock outputs default LOW when inputs open
Multiplexed clock input
Internal 300kohms pullup resistor on input pins
CLK & CLK have 110-ohm internal termination (PI90LVT14)
50ps Output-to-Output Skew
475ps typical propagation delay
±22ps Period Jitter
Bus Pins are high impedance when disabled or with VCC less
than 1.5V
TTL inputs are 5V Tolerant
Power Dissipation at 400Mbits/s of 150mW
Function compatible to Motorola (PECL)
MC100EL14 and Micrel/Synergy (PECL)
SY100EL14V
>9kV ESD Protection
20-pin TSSOP (L) and QSOP (Q) packages
Pin Descriptions
Pin
CLK, CLK
SCLK
EN
SEL
CLK1-5OUT±
Funtion
Differential Clock Outputs
LVTTL Clock Input
Synchronous Enable
Clock Select Input
Differential Clock Inputs
Function Table
CLK SCLK SEL
EN*
L
X
L
L
H
X
L
L
X
L
H
L
X
H
H
L
↓
↓
X
H
* On next negative transition of CLK, or SCLK
CLKOUT+
L
H
L
H
Z*
Description
The PI90LV14 implements low voltage differential signaling (LVDS)
to achieve clocking rates as high as 320MHz with low skew.
The PI90LV14 is a low-skew 1:5 clock distribution chip which
incorporates multiplexed clock inputs to allow for distribution of a
lower-speed, single-ended clock or a high-speed system clock.
When LOWthe SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. Because the internal flip-flop is clocked on the falling edge
of the input clock, all associated specification limits are referenced
to the negative edge of the clock input.
The intended application of these devices and signaling technique
is for high-speed clock distribution between boards.
PI90LV14 Block Diagram
CLK1OUT+
1
2
CLK1OUT–
CLK2OUT+
3
4
CLK2OUT–
CLK3OUT+
5
6
CLK3OUT–
CLK4OUT+
7
8
CLK4OUT–
CLK5OUT+
9
CLK5OUT– 10
D
Q
20 VCC
19
EN
18 VCC
17 GND
1
16 SCLK
15
CLK
110Ω
PI90LVT14
Only
0
14
CLK
13 GND
12 SEL
11 GND
1
PS8538A 09/11/01
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